1. Field of the Invention
The present invention relates to a liquid crystal display module, and more particularly to a chip-mounted film package of the liquid crystal display module.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) employs an electric field to control light transmittance through a liquid crystal having a dielectric anisotropy, thereby displaying a picture. Specifically, the LCD includes an LCD panel for displaying a picture, and a driving circuit for driving the LCD panel. In the LCD panel, liquid crystal cells are arranged in a matrix to control light transmittance in accordance with pixel signals, thereby displaying a picture. The driving circuit includes a gate driver for driving gate lines of the LCD panel, a data driver for driving the data lines, a timing controller for controlling a driving timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the LCD panel and the driving circuit.
The data driver and the gate driver are separated into a plurality of drive integrated circuits (D-ICs). Each of the D-ICs is mounted on an opened IC area of a tape carrier package (TCP) or on a base film of the TCP by a chip on film (COF) system, to thereby be electrically connected to the LCD panel by a tape automated bonding (TAB) system. Alternatively, the D-IC may be directly mounted on the LCD panel by a chip on glass (COG) system. Since the TAB system ensures that a relatively wide pixel matrix area from the LCD panel has an easy attachment process, it has been mainly used.
FIG. 1 is a plan view schematically illustrating a rear structure of a related art LCD module. As shown in FIG. 1, the related art LCD module includes a data TCP (or COF) 12 and a gate TCP (or COF) 16. The data TCP 12 (or COF) is connected between a data PCB 20 and an LCD panel 10 and has a data D-IC 14 mounted thereon. On the other hand, the gate TCP (or COF) 16 is connected between a gate PCB 22 and the LCD panel 10 and has a gate C-IC 18 mounted thereon.
The LCD panel 10 has a thin film transistor array substrate and a color filter array substrate that are bonded to each other with a liquid crystal layer therebetween. The LCD panel 10 includes liquid crystal cells between gate lines and data lines. Each of the liquid crystal cells includes a thin film transistor as a switching device. The thin film transistor applies a pixel signal from the data line in response to a scanning signal from the gate line.
The data D-IC 14 is connected to the data line of the LCD panel 10 via the data TCP (or COF) 12. The data D-IC 14 converts a digital pixel data signal from an external timing controller (not shown) into an analog pixel signal and applies the analog pixel signal to the data line. On the other hand, the gate D-IC 18 is connected to the gate line of the LCD panel 10 via the gate TCP (or COF) 16. The gate D-IC 10 supplies a turn-on voltage of the thin film transistor to the gate line during a corresponding scan period while supplying a turn-off voltage of the thin film transistor to the gate line during the remaining period.
The data TCP (or COF) 12 and the gate TCP(or COF) 16 shown in FIG. 1 are prepared on a roll-type base TCP and then are molded by a cutting process. FIG. 2 is a plan view showing the data TCP (or COF) 12 before the cutting process of the related art LCD module. As shown in FIG. 2, the data TCP (or COF) 12 is provided on a base film 32 of the roll-type base TCP 30. The base film 32 is usually made of polyimide. The data TCP (or COF) 12 has the data D-IC 14 mounted thereon, and is also provided with a plurality of input pads IP connected to input pins of the data D-IC 14 and a plurality of output pads OP connected to output pins thereof. Further, a sprocket hole 34 is provided in a line along the vertical direction at each side of the base film 32 so as to deliver the base film 32 and determine a delivery position.
The data TCP (or COF) 12 is molded by a process of cutting the base TCP 30 along a cutting line CL. The molded data TCP (or COF) 12 is attached to the LCD panel 10 shown in FIG. 1 and to the data PCB 20 by an anisotropic conductive film ACF. A first aligning mark 15 adjacent to the input pad IP is provided within the data TCP (or COF) 12 so as to make an alignment of the data TCP (or COF) 12 with the data PCB 20. A second aligning mark 17 adjacent to the output pad OP is provided within the data TCP (or COF) 12 so as to make an alignment of the data TCP (or COF) 12 with the LCD panel 10.
The data TCP (or COF) 12 is provided on the base TCP 32 generally having a normal horizontal width of 35 mm as shown in FIG. 2 such that the data TCP (or COF) 12 has 384 output pads OP, namely, 384 output channels in light of manufacturing costs. In this case, the data TCP (or COF) 12 has an effective horizontal width of about 27 mm excluding a dummy area where the sprocket hole 34 are formed on the base TCP 30. Moreover, the 384 output pads OP of the data TCP(or COF) 12 are provided in parallel to each other at a pitch P1 of about 60 μm in light of reliability and process tolerance. The 384 output channels of the data TCP (or COF) 12 correspond to output channels of the data D-IC 14.
In order to reduce manufacturing costs by reducing the number of the data TCP (or COF) 12 and the data D-IC 14 that are expensive, the number of the output channels of the data TCP (or COF) 12 and the data D-IC 14 should be increased. For instance, when the LCD panel 10 has a XGA class resolution of 1024×768 pixels, it is provided with total 3072 data lines in light of R, G and B sub-pixel included per pixel. If the 3072 data lines are intended to be driven by the data D-IC 14 having the 384 output channels shown in FIG. 2, then the LCD panel 10 of FIG. 1 must include 8 (i.e., 3072/384=8) data D-ICs 14 and 8 data TCPs (or COFs) 12 mounted with them. However, the data D-IC 14 includes a digital to analog converter (DAC) having a complex structure proportional to the number of data lines in order to convert 6-bit or 8-bit pixel data supplied per data line into analog pixel signals. Thus, once the number of the output channels of the data D-ICs 14 is increased, the circuit structure becomes complex and difficult to enlarge a chip area as well as an area of the data TCP (or COF) 12 mounted with the data D-IC 14. Moreover, the TCP (or COF) has a relatively high cost with respect to an area thereof. Thus, there is a problem in that, once the number of the output channels of the data D-IC 14 is increased, an area of the TCP (or COF) is enlarged, which makes the manufacturing costs rise more.
In order to overcome this problem, a proposal has been made to reduce an area occupied by the DAC circuit by using a time-divisional driving of the data lines so as to increase the number of output channels of the data D-ICs while controlling the chip area, thereby reducing the number of the D-ICs and TCPs, as disclosed in Korea Patent Application No. 2002-41769. However, since the number of the output channels of the data D-ICs are increased by twice when the number of the data D-ICs is reduced to a half (½) and hence an area occupied by the output pads instead of the D-ICs is enlarged, it becomes necessary to provide a base TCP having a larger dimension than the existent 35 mm base TCP. Moreover if a 70 mm TCP instead of the 35 mm TCP is used for the purpose of increasing the number of the output channels per TCP by twice, then there is a problem in that an expensive TCP also leads to an increase of the manufacturing costs.
In order to solve this problem, a strategy has been proposed to reduce a distance between the output channels within the TCP (or COF) to increase the number of output channel per unit area. However, this strategy has a limitation in that reducing a distance between the output pads can only be done to certain degree in light of reliability and manufacturing process tolerances. Moreover, an effective area to be occupied by the data TCP (or COF) 12 is further reduced even on the 35 mm base TCP 30 as shown in FIG. 2 due to the dummy area for forming the sprocket holes 34 to thereby have a horizontal width of about 27 mm. As a result, the data TCP (or COF) 12 having an effective horizontal width of 27 mm as shown in FIG. 2 is limited to an increase of 384 output pads OP provided at a pitch P1 of about 60 μm, that is, the number of the output channels.
Therefore, there is a desire to enlarge an effective area of the data TCP (or COF) 12 without enlarging the base TCP (or COF), which adversely affects the manufacturing costs, thereby increasing the number of the output channels.